Technical work from Avenstride Labs.
We publish methods, experiments, and measured limits from our hardware engineering research.
Papers
0401Human routes
→02Neural signal
→03Heuristic update
→04Verified routing
Paper 001July 2026
Neural-guided optimization of deterministic schematic routing heuristics
A neural preference model guides the optimization of an auditable heuristic router. Deterministic validation continues to protect electrical correctness.
Read paper →120parsed schematics
remove routerestore reference
G=G'
graph admission342safe tasks
Paper 002July 2026
Graph-safe reconstruction benchmarks for schematic routing
A conservative task-extraction method uses human geometry while protecting electrical label integrity with graph-equivalence checks.
Read paper →candidateU?
collisionU?
selectedU7
0.772mean similarity
Paper 003July 2026
Wire-aware component placement for generated schematics
Component positions are evaluated with spatial, electrical, relational, and route-feasibility terms before selection.
Read paper →generated schematic
Axis AGraphhash match
Axis BGeometrygrid and clearance
AND
Acceptboth gates pass
Paper 004July 2026
Two-axis validation for generated schematics
Electrical graph equivalence and geometric acceptance remain independent requirements for generated CAD artifacts.
Read paper →